Patent Documents 1 and 2 disclose an output buffer equipped with de-emphasis function in which the amplitude of an output signal emphasized when the logic of the output signal is changed, is attenuated when the logic of the output signal following the change remains unchanged. Patent document 1 discloses a configuration including a main buffer, a delay circuit, an emphasis driver, and a subtracter composed of a differential circuit. Patent Document 2 discloses an emphasis circuit constituted by a CMOS inverter, with a configuration including a tri-state buffer that performs switching control to determine whether to activate the emphasis function based on the control signal.
FIG. 5 is a diagram showing the configuration of an output buffer circuit equipped with a conventional de-emphasis function. For the sake of description, the following describes an exemplary configuration in which the ENABLE signal is introduced into the configuration (differential circuit), described in Patent Document 1, as the control signal for activating the emphasis function. Patent Documents 1 and 2 disclose an output buffer having the pre-emphasis function, which emphasizes the amplitude at the transition bit when the logic of the signal is changed, and the de-emphasis function which decreases the emphasized amplitude when the logic of the bits following the transition bit is not changed. The following describes an output buffer with the de-emphasis function that outputs the amplitude defined by the power supply potential VDD in the transition bit and decreases the amplitude when the logic of the bit following the transition bit is not changed.
Referring to FIG. 5, the output buffer circuit comprises differential input terminals (INP/INN) that differentially receive a data signal; a main-data pre-buffer 53 that receives the differential signal input at the differential input terminals (INP/INN); a main-data main buffer 51 that receives a differential output (main-data) 57 from the main-data pre-buffer 53; a delay circuit 55 that receives the differential signal input at the differential input terminals (INP/INN), delays the signal, and differentially outputs the delayed signal; a de-emphasis pre-buffer 54 that differentially receives a differential output 56 from the delay circuit 55; and a de-emphasis main buffer 52 that differentially receives a differential output (de-emphasis data) 58 from the de-emphasis pre-buffer 54. The non-inverting output (positive) from the main-data main buffer 51 and the inverting output (negative; indicated by a circle) from the de-emphasis main buffer 52 are connected in common to a non-inverting output terminal OUTP. The inverting output (negative; indicated by a circle) from the main-data main buffer 51 and the non-inverting output (positive) from the de-emphasis main buffer 52 are connected in common to an inverting output terminal OUTN. The de-emphasis pre-buffer 54 and the de-emphasis main buffer 52 become active and operable when they receive the control signal ENABLE that is active, and becomes inactive when the control signal ENABLE is inactive.
The main-data main buffer 51 and the de-emphasis main buffer 52 emphasize the amplitude of a signal for output when the signal to be output (OUTP/OUTN) undergoes the change of the logic.
When de-emphasis is disabled, the control signal ENABLE deactivates the de-emphasis main buffer 52 and the de-emphasis pre-buffer 54. In this case, the main-data main buffer 51 drives a transmission line alone (balanced transmission line connected to OUTP and OUTN). For this reason, the main data main buffer 51 is adapted to have a driving capability for driving the transmission line.
The amplitude of the transition bit, which is the first bit signal immediately after the logic of the signal output from the output terminals (a pair of differential output terminals) (OUTP/OUTN) is changed, is fixed regardless of whether de-emphasis is enabled or disabled.
The waveform is emphasized by attenuating the amplitude of non-transition bits that are the signals following the transition bit. For example, when the output signal level VOH of the transition bit, generated immediately after the signal level is changed from low to high, is the power supply potential VDD and the following bit (non-transition bit) is high, the amplitude VOH of this signal is set lower than VDD. When the output signal level VOL of the transition bit, generated immediately after the signal level is changed from high to low, is the GND level and the following bit (non-transition bit) is low, the amplitude VOL of this signal is raised higher than GND.
FIG. 6 is a diagram showing an example of the configuration of the main buffer 50 composed by the main-data main buffer 51 and the de-emphasis main buffer 52 shown in FIG. 5. In FIG. 6, the buffer 51 in FIG. 5 corresponds to a circuit 20 and the buffer 52 in FIG. 5 corresponds to circuit 21.
Referring to FIG. 6, the configuration comprises N-channel MOS transistors 22 and 23 which have sources connected in common to a constant current source I1 (current value is variably controlled) and which have gates for receiving the non-inverting signal (Main data positive) and the inverting signal (Main data negative) of the main data 57 in FIG. 5 respectively; and N-channel MOS transistors 24 and 25 which have sources connected in common to a constant current source I2 (current value is variably controlled) and which have gates for receiving the non-inverting signal (Emphasis data positive) and the inverting signal (Emphasis data negative) of the emphasis data 58 in FIG. 5 respectively. The drain of the transistor 22 and the drain of the transistor 25 are connected in common to the inverting terminal OUTN and, via a resistor R1, connected to the power supply VDD, and the drain of the transistor 23 and the drain of the transistor 24 are connected in common to the non-inverting terminal OUTP and, via a resistor R2, connected to the power supply VDD. The constant current source I2 and a switch SW are connected in series between the coupled source of the N-channel MOS transistors 24 and 25 and the ground and, when emphasis is disabled, the control signal ENABLE is inactive and the switch SW is off. The following describes the operation when emphasis is enabled (control signal ENABLE is active and switch SW is on). In the description below, a high level is a logic value 1, and a low level is a logic value 0.
When the non-inverting signal and the inverting signal of the main data 57 are 1 and 0 and the non-inverting signal and the inverting signal of the emphasis data 58 are 0 and 1 (non-inverting signal of main data 57 is the transition bit that changes from 0 to 1), the transistors 22 and 25 whose drains are connected in common are turned on, the transistors 23 and 24 are turned off, and the current corresponding to the sum of the currents of the current sources I1 and I2 flows through the resistor R1. OUTN=VDD−(I1+I2)×R1 and OUTP=VDD and the amplitude of the output signal is OUTP−OUTN=(I1+I2)×R1.
When the non-inverting signal and the inverting signal of the main data 57 are 1 and 0 and the non-inverting signal and the inverting signal of the emphasis data 58 are 1 and 0, the transistors 22 and 24 are turned on, the transistors 23 and 25 are turned off, and the currents corresponding to I1 and I2 flow through the resistors R1 and R2, respectively. Because the voltage difference between OUTP and OUTN is calculated from OUTN=VDD−R1×I1 and OUTP=VDD−R2×I2, the amplitude of the output signal is OUTP−OUTN=R1×I1−R2×I2. When R1=R2=R, OUTP−OUTN=R×(I1−I2) and the circuit in FIG. 6 becomes a subtraction circuit. The amplitude of OUTP−OUTN becomes smaller than that of the transition bit ((I1+I2)×R1), indicating that de-emphasis is performed.
When the non-inverting signal and the inverting signal of the main data 57 are 0 and 1 and the non-inverting signal and the inverting signal of the emphasis data 58 are 1 and 0 (non-inverting signal of main data 57 is the transition bit that changes from 1 to 0), the transistors 23 and 24 are turned on, the transistors 22 and 25 are turned off, and the current corresponding to the sum of the currents of I1 and I2 flows through the resistor R2. OUTP=VDD−(I1+I2)×R2 and OUTN=VDD and the amplitude of the output signal is OUTP−OUTN=−(I1+I2)×R2.
When the non-inverting signal and the inverting signal of the main data 57 are 0 and 1 and the non-inverting signal and the inverting signal of the emphasis data 58 are 0 and 1, the transistors 23 and 25 are turned on, the transistors 22 and 24 are turned off, and the currents corresponding to I2 and I1 flow through the resistors R1 and R2, respectively. Because the voltage difference between OUTP and OUTN is calculated from OUTN=VDD−R1×I2 and OUTP=VDD−R2×I1, the amplitude of the output signal is OUTP−OUTN=R1×I2−R2×I1. When R1=R2=R, OUTP−OUTN=R×(I2−I1) and the circuit in FIG. 6 becomes a subtraction circuit. The amplitude of OUTP−OUTN becomes smaller than that of the transition bit, indicating that de-emphasis is performed.
When emphasis is disabled, the differential circuit 21 is inactive and only the differential circuit 20 is active.
When the de-emphasis is enabled, the currents that flow through the constant current sources I1 and I2, respectively have current values having a relationship of a ratio determined by a de-emphasis level. When the de-emphasis is disabled, a current for driving the transmission line flows through the current source I1 alone, and no current flows through the constant current source I2.
Then, when a circuit configuration is made in which the amplitude of the transition bit becomes the same in both cases where the de-emphasis is enabled and where the de-emphasis is disabled, the sum of the currents from the constant current source I1 and the constant current source I2 when the de-emphasis is enabled is controlled to be equal to the value of the current from the constant current source I1 when the de-emphasis is disabled. When the de-emphasis is disabled (the circuit 21 is inactive), for example, the current value of the constant current source I1 of the circuit 20 is adjustably controlled to become equal to a sum value I of the currents of the constant current source I1 and the constant current source I2 at the time of the de-emphasis being enabled.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P-2004-88693A
[Patent Document 2]
JP Patent Kokai Publication No. JP-P-2002-94365A